Electrographic apparatus

ABSTRACT

The electrographic apparatus of a variety wherein a transparent resistive layer is deposited upon an insulative substrate in a manner wherein a rectangularly-shaped resistive layer region is developed having a predetermined conductivity. A conduction band is provided about the periphery of the resistive layer region having a value of conductivity enhanced with respect to the conductivity value of the resistive layer. Discrete resistive elements are positioned intermediate the conduction band and the resistive region and four terminals are provided, one at each of the four corners of the rectangular resistance region. The discrete resistance elements are designed so that a uniform impedance is witnessed with respect to the resistive layer region as witnessed with respect to each of the four terminals. The control system for the device provides for development of coordinate pair information and includes as non-volatile memory retained configurational data for initial set-up of the apparatus by the operator.

BACKGROUND OF THE INVENTION

Electrographic devices in which coordinate pair signals are generated bymanual positioning of a locator or the like upon an operative surfacehave become subjects of increasing popularity both to industry andwithin the consumer market. Industrial demands for the devices haveoccurred in conjunction with the evolution of computer graphics,computer aided design, and computer aided manufacturing systems. Asthese systems have been improved, a need has been observed for combininghte digitizer funcction with a visual readout such that the operationalaspects of vision and information input may be combined to perform inconcert before the operator. In the latter regard, an outgrowth of thiscombination of htese function sresides in the electronic notepad or htelike wherein business forms and the like established at a display outputmay be "filled in" employing a stylus or cursor and in conjunction withcharacter recognition software. For these advanced aspects ofcomputerized graphics information systems to achieve practicality, thedigitizer components of the system must be fabricable on a practicalbasis with minimal electronic supporting bulk, high noise immunity, highresolution and accuracy and at cost levels commensurate with therelatively higher volume applications contemplated.

The operation of a classic digitizer or graphics tablet has generallyinvolved the utilization by an operator of a stylus or tracer locatingdevice representing a writing instrument which is positioned upon theoperational surface and moved across it in some electrical association.The electrographic device responds to the position of this locatingstylus or tracer to generate paired analog coordinate signals which aredigitized and conveyed to a computer facility. For electronic notepadapplications, the computer respojndst othe paired coordinate signals togenerate a pixel at a display positioned immediately adjacent thedigitizer surface and at the location of the stylus or tracer. As isapparent, high resolution capabilities are required for suchapplications.

Early approaches to digitizer structures looked to arrangements whereina grid formed of two spaced arrays of mutually, orthogonally disposedfine wires are embedded in an insulative carrier. One surface of thisstructure serves to yieldably receiuve a stylus input which yieldingcauses the grid components to intersect and read out coordinate signals.More recent and improved approaches to achieving readouts have beenaccomplished through resort to a capacitive coupling of the stylus orlocating instrument with the position responsive surface to generatepaired analog coordinate signals. Such capacitive coupling can becarried out either with a grid layer which is formed of spaced lineararrays of conductors or through resort to the use of an electricallyresistive material layer or coating.

Particularly where applications of combining the digitizer surface witha visual readout are contemplated, the provision of the digitizersurface as a somewhat continuous resistive material shows immediateapparent advantage. Such transparent coatings additionally may beemployed with digitizer tablets which are placed over drawings,photographic material, or the like for tracing profiles and generatingcomputer data corresponding therewith.

A variety of technical problems have been encountered in the developmentof an effective resistive coating type digitizer technology, one ofwhich concerns the non-uniform nature of the coordinate readoutsreceived from the surfaces. Generally, precise one-to-one correspondenceor linearity is required between the actual stylus or tracer positionand the resultant coordinate signals. Because the resistive coatingscannot be practically developed without local resistance (thickness)variations the nonlinear aspects of the otherwise promising approachhave required a considerable amount of inventigation and development. Anearlier development in this regard is described by Turner in U.S. Pat.No. 3,699,439 entitled "Electrical Probe-Position Responsive Apparatusand Method" issued Oct. 17, 1972, and assigned in common herewith. Thisapproach uses a direct current form of input to the resistor surfacefrom a hand-held stylus, the tip of which is physically applied to theresistive surface. Schlosser, et al. in U.S. Pat. No. 4,456,787,entitled "Electrographic System and Method", issued June 26, 1984, alsoassigned in common herewith, describes the employment of an a.c. inputsignal in conjunction with such devices as well as the signal treatmentof the resulting coordinate pair output signal. A voltage waveform zerocrossing approach has been suggested by Turner to improve resolution inU.S. Pat. No. 4,055,726 entitled "Electrical Position Resulting byZero-Crossing Delay" issued Oct. 25, 1977, and assigned in commonherewith. Kable, in U.S. Pat. No. 4,600,807, issued July 15, 1986, andassigned in common herewith, describes a successful signal treatmenttechnique for transparent digitizer systems. In general, this approachutilizes a plurality of switches along the four coordinate borders ofthe tablet structure. An a.c. drive signal is applied from one border,while the opposite border is retained at ground for a given coordinatereadout, for example in the x-axis direction. Plus and minus values aredeveloped for generating x-coordinate pairs as well as y-coordinate paisand during the evaluation process, those switches aligned along theborders not being used at ground or as drivers are retained in a"floating" condition. Thus the switching employed with such digitizingapproaches exhibit three states for a given coordinate generatingoperation. In general, the utilization of a third or floating state withthese switches has been the subject of some noise generation. Inasmuchas the switches are receptive to flowing currents within the digitizersurfaces during such time as they are in a floating state, any thermalresponses ofthe switching components themselves will be reflected in tehoverall signal process. Avoidance of this state for such switches aswell as the relatively large requisite number of switches now employedin digitizer assemblages will be of considerable advantage in achievingimproved operation and desired simplicity.

Substantially improved accuracies for the resistive surface typedigitizing devices have been achieved through a correction procedurewherein memory retained correction data are employed with the digitizersuch that any given pair of coordinate signals are corrected inaccordance with data collected with respect to each digitizer resitivesurface unit during its manufacture. With such an arrangement, the speedof correction is made practical and the accuracy of the devices issignificantly improved. Such correction process is described byNakamura, et al., in U.S. Pat. No. 4,650,926, issued Mar. 17, 1987, andassigned in common herewith.

In order to avoid interference from externally generated noise, handeffects, and the like, the resistivity for transparent digitizerspreferably falls within predetermined acceptable ranges, for example,between 400 and 3,000 ohms per square. To achieve the higher levels ofresistivity thus desired, very thin resistive coatings, for example ofindium tin oxide (ITO) have been employed. However, it has been observedthat, over a period of time, surface effects and the like will affectthe resistivity values of a given tablet occasioning an unwanted "drift"in such value to affect long term accuracy. To improve the long termstability of the coatings, thicker coatings have been employed incombination with discontinuities in the layer itself as described byKable, et al., in U.S. Pat. No. 4,665,283, issued May 12, 1987, andassigned in common herewith. Improvements in performance also have beenachieved through the utilization of angular shaped electrodes at cornerpositions as well as a conductive band or band of enhanced conductivitywhich is positioned intermediate the outer periphery of the digitizerdevice and the active area thereof as described by Nakamura, et al., inU.S. Pat. No. 4,649,232 entitled "Electrographic Apparatus" and assignedin common herewith.

Improvements in the locators or pick-up devices themselves utilized withdigitizers have been evolved to enhance overall performance of thesystems. For example, an improved tracer or cursor is described by Kableet al. in U.S. Pat. No. 4,707,572, entitled "Tracer for ElectrographicSurfaces" issued Nov. 17, 1987, assigned in common herewith. Similarly,Kable describes an improved stylus structure in U.S. Pat. No. 4,695,680,entitled "Stylus for Position Responsive Apparatus Having ElectrographicApplication" issued Sept. 22, 1987, and assigned in common herewith.

SUMMARY

The present invention is addressed to electrographic apparatus forgenerating coordinate data which exhibits significantly improveddistortion control to an extent permitting important simplification ofits electronic control architecture. The apparatus, system and methodincorporates a boundary configuration which, while achieving importantaspects of distortion control, does so without undue loss of operationalsurface. As a consequence, a broad range of practical applications ofthe resultant technology becomes available, not only in connection withdigitizer tablets per se, but also for such applications as electronicnotepads and the like.

With the improvements of the invention, the number of solid-stateswitching components required about the border of the resistive surfaceis substantially reduced. Such switching functions need no longer be ofa three-state (ground, signal transfer and floating) configuration, andmay ideally be operated in noise immune configurations to improveoverall performance of the electrographic devices.

In one embodiment of the invention, enhanced coordinate data generationis achieved through simultaneous application of dual frequencies to thedigitizer surface. Such higher rates of data development may findapplication, for example, in electronic handwriting applications and thelike.

Another particular feature of the invention is to provide apparatus ofthe type wherein a surface is selectively accessed with respect topositional data which includes an insulative substrate and a resistivelayer supported upon the substrate having an operational regionextending within a operational periphery of predetermined geometricpattern and configured to exhibit predetermined values of theconductivity and resistivity, the operational periphery being spacedinwardly from the outer boundary. Terminals are mutually spaced andsupported upon the substrate, and positioned adjacent the outer boundaryas well as at the corners of the geometric pattern. An arrangementdefining a conduction band exhibiting enhanced conductivity wiht respectto the operational region conductivity is supported upon the substrateintermediate the outer boundary and the operational periphery and aplurality of spaced, discrete resistance elements, each in electricalcommunication intermediate the conduction band and the resistive layereach having a resistance value selected to effect exhibition ofsubstantially uniform electrical impedance of the layer to each terminalare provided. Further provided is an excitation signal source as well asa ground reference and a switch arrangement which is actuable forapplying the ground reference to first select ones of the terminalswhile simultaneously applying the excitation signal source to secondones of the terminals oppositely disposed from the first ones and acontrol serves toa ctuate the switches to effect derivation ofpositional data modes.

Another feature of the invention is to provide apparatus of the typewherein the surface is selectively accessed with respect to positionaldata which includes an insulative substrate serving to support aresistive layer having an operational region extending within anoperational periphery and configured to exhibit predetermined values ofconductivity and resistivity. The operational periphery is spacedinwardly from the outer boundary. Mutuall spaced terminals are supportedon the substrate and are positioned adjacent the outer boundary and thecorners of a predetermined geometric pattern of the noted operationalperiphery to develop positional data modes. A conduction band exhibitingenhanced conductivity with respect to the operational regionconductivity is supported upon the substrate intermediate the outerboundary and the operational periphery. A plurality of spaced, discreteresistance elements, each in electrical communication intermediate theconduction band and the resistive layer are provided wherein each has aresistance of value selected to effect exhibition of a substantiallyuniform electrical impedance of the layer to each terminal. A timevarying excitation signal source is provided for deriving the firstsignal at a first select frequency and a second signal at a secondselect frequency. Switches are provided which are actuable for applyingthe first signal to first select ones of the terminasl whilesimultaneously applying the second signal to second select ones of theterminals oppositely disposed from the first ones and a control servesto actuate the switches to effect derivation of positional data modes.

Still another feature of the invention is to provide electrographicapparatus which includes an insulative substrate and a resistive layersupported upon the substrate and extending in an x-coordinate sensebetween first parallel, spaced-apart borders and in a y-coordinate sensebetween second parallel, spaced-apart border to provide a rectangularresistive layer regionhaving four corners and configured to exhibitpredetermined values of resistivity and conductivity, the resistivelayer region being spaced inwardly from an outer boundary. A terminal issupported upon the substrate adjacent the outer boundary for interactionwith the resistive layer region at each of the noted corners and anelongate conduction band exhibiting predetermined enhanced conductivitywith respect to the conductivity of the resistive layer region issupported upon the substrate intermediate the outer boundary and thefirst and second parallel, spaced-apart borders. A plurality of disrete,spaced, resistance elements, each in electrical communicationintermediate the conduction band and the resistive layer region, andeach having a value of resistance selected to effect exhibition of asubstantially uniform electrical impedance of the region to eachterminal are provided. Further provided is an excitation signal sourceand a ground reference. A switch arrangement is coupled with theterminals, the source and the ground reference, and is actuable toselectively apply the excitation signal and ground reference to theterminals. A locator is movable into adjacency with the resistance layerfor recting therewith to develop position signals and a control servesto actuate the switches during a first data mode to apply the groundreference and excitation signal to first and second pairs of therterminals selected in an x-coordinate sense and to apply the groundreference and excitation signal to third and fourth pairs of theterminals selected in y-coordinate sense during a second data mode. Thecontrol includes signal treatment features which respond to the positionsignals derived during the first and second data modes for derivingrespective x-coordinate and y-coordinate signals.

Another feature of the invention provides electrographic apparatus whichincludes an insulative substrate and a resistive layer supported uponthe substrate and extending in an x-coordinate sense between firstparallel, spaced-apart borders and in a y-coordinate sense betweensecond parallel, spaced-apart borders to provide a rectangular resistivelayer region having four corners and configured to exhibit predeterminedvalues of resistivity and conductivity, the resistive layer region beingspaced inwardly from an outer boundary. A terminal is supported upon thesubstrate adjacent the outer boundary for interaction with the resistivelayer region at each corner. An elongate conduction band exhibitingenhanced conductivity with respect to the conductivity of the resistivelayer region is supported upon the substrate intermediate the outerboundary and the first and second parallel, spaced-apart borders. Aplurality of discrete, spaced resistive elements, each in electricalcommunication intermediate the conduction band and the resistive layerregion, and each having a value of resistance selected to effectexhibition of substantially uniform electrical impedance of the regionwith respect to each terminal are provided. An excitation signal sourcederiving a first signal at a first select frequency and a second signalat a second select frequency is provided along with switches coupledwith the terminals as well as with the source and are actuable toselectively apply the first and second excitation signals to theterminals. A locator is movable into adjacency with the resistive layerfor reacting therewith to develop position signals at the first andsecdon signals to third and fourth pairs of the terminals selected inthe y-coordinate sense during a second data mode. The control furtherincludse a signal treatment arrangement responsive to the positionsignal derived during the first and second data modes for derivingrespective x-coordinate and y-coordinate signals.

A further feature of the invention is to provide apparatus of a typewherein a surface is selectively accessed with respect to positionaldata which includes an insulative substrate and a resistive layersupported upon a substrate having operational region extending within anoperational periphery of predetermined geometric patterna dn configuredto exhibit predetermined value of conductivity and resistivity. Theoperational perihery is spaced inwardly from the outer boundary.Mutually spaced terminals are supported upon the substrate and arepositioned adjacent the outer boundary as well as the corners of thegeometric pattern and a conduction band exhibiting enhanced conductivitywith respect to the operational region conductivity is supported uponthe substrate intermediate the outer boundary and the operationalperiphery. A plurality of spaced discrete resistance elements, each inelectrical communication intermediate resistance of value selected toeffect exhibition of a substantially uniform electrical impedance of thelayer to each terminal. An excitation signal source is provided as wellas a locator coupled with the excitation signal source and movalbe intoadjacency with the resistive layer for applying the source thereto at aselect position. A current-to-voltage converter is coupled with each ofthe terminals and exhibits a virtual ground thereto and has positionoutput signals in response to the source application by the locator.Switches are actuable for collecting select position output signals inaccordance with predetermined positional data modes and a control servesto actuate the switches in accordance with the data modes and fortreating the collected poistion output signals toderive x- andy-coordinate signals corresponding with the locator select location.

Another feature of the invention is to provide electrographic apparatuswhich includes an insulative substrate which serves to support aresistive layer and which extends in an x-coordinate sense between firstparallel, spaced-apart borders and in a y-coordinate snese betweensecond parallel, spaced-apart borders to provide a rectangular resistivelayer region having four corners and configured to exhibit predeterminedvalues of resistivity and conductivity. The resistive layer region isspaced inwardly from an outer boundary. A terminal is supported upon thesubstrate adjacent the outer boundary for interaction with the resistivelayer region of each corner. An elongate conduction band exhibitingenhanced conductivity with respect to the conductivity of the resistivelayer region is supported upon the substrate intermediate the outerboundary and the first and second parallel, spaced-apart borders. Aplurality of discrete, spaced resistance elements, each in electricalcommunication intermediate the conduction band in the resistive layerregion and each having a value of resistance selected to effectexhibition of substantially uniform electrical impendance of the regionto each terminal are provided. An excitation signal source is furtherprovided as well as a locator which is coupled with the excitationsignal source and is movable into adjacency with the resistive layer forreacting in signal transfer relationship therewith at a select location.A current-to-voltage converter is coupled with each terminal whichexhibits a virtual ground thereto and provides position output signalsin response to the locator means reaction. Switches are actuable forcollecting select position output signals and a control serves toactuate the switches during a first data mode to effect collection ofthe position output signals from first and second pairs of the terminalsselected in the x-coordinate sense and to effect collection of theposition output signals from third and fourth pairs of the terminalsselected in the y-coordinate sense during a second data mode. Thecontrol includes a signal treatment arrangement which is responsive tothe collected position signals derived during the first and second datamodes for deriving respective x-coordinate and y-coordinate signals.

Other objects of the invention will, in part, be obvious and will,inpart, appear hereinafter.

The invention, accordingly, comprises the apparatus possessing theconstruction, combination of elements, and arrangement of parts whichare exemplified in the following detailed disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic representation of a one-dimensional model of theelectrographic apparatus of the invention;

FIG. 2 is a schematic equivalent circuit of the model of FIG. 1;

FIG. 3 is a schematic idealized curve showing voltage distributionacross the resistive layer represented in FIG. 1;

FIG. 4 is a top view of an electrographic digitizer tablet according tothe invention;

FIG. 5 is a partial top view of the electrographic tablet of FIG. 4showing resistive layer patterns, conduction band structure, anddiscrete resistance elements employed with the device;

FIG. 6 is a schematic representation showing the circuit and switchingcomponents of a preferred embodiment of the instant invention;

FIGS. 7 through 10 are computer model representations of the read-outfor an electrographic device having a ratio of conductivity of aconduction band according to the invention to the resistive layer regionof 25:1 and wherein the values of discrete resistance elements arevaried to achieve a linear response;

FIG. 11 is a computer modeled readout develped as with the readouts ofFIGS. 7-10 but having a conduction band to resistance layer regionconductivity ratio of 50:1;

FIG. 12 is an electrical schematic diagram showing analog treatment ofdigitizer derived signals;

FIG. 13 is an electrical schematic diagram showing the development anddistribution of excitation signals used with the electrographic deviceof the invention;

FIGS. 14A and 14B combine to show an electrical schematic diagramillustrating control circuit components of the electrographic device ofthe invention;

FIGS. 15A-15C constitute a flow chart describing the main controlprogram of the apparatus of the invention;

FIG. 16 is a diagrammatic representation of a menu tree structure usedwith the control program of the invention; and

FIGS. 17A and 17B constitute a flow chart describing an interruptroutine employed with the control progam of the invention.

FIG. 18 is a schematic representation showing the circuit and switchingcomponents of another embodiment of the instant invention.

DETAILED DESCRIPTION

As a preliminary consideration of the general approach taken withresistive surface electrographic technology, reference is made to FIGS.1 and 3 wherein an idealized one-dimensional model is revealed. In FIG.1, an insulative substrate 10 such as glass or the like is shownsupporting a resistive layer of, for example, indium-tin oxide 12.Electrodes 14 and 16 are shown coupled to the resistive layer 12 at theopposite ends or borders thereof. Electrode 14 is coupled with an a.c.source designated V₀ from line 18, while electrode 16 is coupled toground through line 20. A pick-up or locator such as the stylus 22 ispositioned adjacent or in contact with the resistive layer 12 at anygiven location and for example through capacitive coupling serves topick-up a voltage output at line 24, such voltage being labelledV_(sense). The equivalent circuit for this idealized one-dimensionalmodel is represented in FIG. 2 where the resistive layer 12 is shown asa resistor and the distance of the stylus 22 from the edge of theresistor closest to the source V₀ is represented as "X" and the distancebetween electrodes 14 and 16 is represented as "D". The fraction ofresistance of layer 12 extant from the source of voltage excitation tothe location, X, may be represented as XR/D, while the distance from thelocation of the stylus 22 to the opposite electrode as at 16 or line 20may be represented as the labelled value (1-X/D)R. The correspondingidealized value for V sense is shown in FIG. 3 as being linear, asrepresented at the curve 26. As a result of a variety of phenomena, suchlinearity becomes an approximation, however, achieveing adequatelinearity prior to the application of necessary electronic treatmentwill be seen to be highly desirable.

To derive signals representing coordinate pairs with respect to theposition of the stylus 22 on the resistive surface 12, measurements ofthe voltage V_(sense) are made along orthogonally disposed axesdesignated x and y. Through the utilization of switching, theapplication of the voltage source as through line 18 and the connectionof ground as through line 20 as shown in FIG. 1 are alternately reversedfor each of the x and y coordinates. With the values thus obtained foreach designated x and y coordinate, a difference/sum voltage ratio isdetermined to obtain a coordinate position signal or coordinate pairsignal. As a somewhat oppositely considered topology, the coordinatepair deriving signal may be applied through the stylus 22 or locatoritself. In that form of arrangement, similar switching takes place,however, receiving voltage to current converters are employed exhibitingvirtual ground which are polled by switching to develop coordinate pairinformation.

Looking to FIG. 4, a digitizer tablet implemention of the electrographictechnology of the invention is represented generally at 30. Such tabletsas at 30, employing this technology, may be developed having a broadvariety of overall shapes and sizes from small and compact to relativelylarge, for example 36 inches by 24 inches. The devices generally arestructured as a patterned layer of indium tin oxide (ITO) which isdeposited over a transparent glass substrate. The borders of the glasssubstrate in a y-coordinate orientation may be observed at 32 and 34,while the outer borders of the glass for the y-coordinate considerationsare seen at 36 and 38. Of course, such borders may take any of a varietyof geometric shapes. The resistive layer which is positioned upon theglass substrate of tablet 30 is transparent and thus not visible, but isdeposited and patterned such that the deposit itself is thick enough toavoid resistivity drift due to surface effets while maintaining desiredresistivity characteristics. Tehcniques for achieving this stability aredescribed in the above-noted U.S. Pat. No. 4,665,283 incorporated hereinby reference. In general, for smaller digitizer tablets having overallboundary size of 12 inches by 12 inches, for example, a generallydesirable value of resistivity of 600 ohms per square is employed alongwith an excitation, for example at 120 KHz. For larger tablets, theresistivity preferably is altered to 900 ohms per square. However, fortypical applications of digitizer tablets, it is desirable to maintainthe resistivity under about 1,000 ohms per square to avoid hand effectsand the like. Also seen in FIG. 4 is a plastic housing 40 which retainsthe circuitry employed in operation of the tablet and this housing 40additionally is seen to support a readout or display 42 which isutilized to prompt the operator in proper set-up of the digitizer foruse with a given computer. In the latter regard, an ouput cable to thecomputer is shown at 44. Also seen in FIG. 4 are linear shapedconductors formed, for example, of a silver ink or the like, whichextend from the circuitry within housing 40 to the corners of theresistive layer deposition or operational periphery of the tablet 30. Inaccordance with the invention, only four corners are primarily accessedby the circuitry of the device. In this regard, an L-shaped electrode orterminal 44 is seen coupled to the circuitry within housing 40 via adeposited thin silver lead 46. In similar fashion, an L-shaped terminal48 is positioned at the upper right corner of the resistive region andis connected to the circuitry of the tablet 30 by thin deposited line50. The lower right corner of the tablet 30 is addressed by an L-shapedterminal 52 which is coupled to the electronics within housing 40 viathin deposited conductive line 54 and, lastly, L-shaped terminal 56 atthe lower left corner of the resistive layer is coupled to theelectronics of housing 40 via deposited thin line or lead 58.

Additionally seen on the surface of the tablet 30 is a rectangularconfiguration of shorting bars which will be seen to be positioned atthe periphery of the resistive layer or surface or operational regionand which are formed as deposited silver lines as are represented at60-63. Additionally shown on the tablet is a non-operational boundarydesignation 64 which is non-functional from an electronic sense butwhich apprises the operator of the desired performance region for usingtablet 30. Generally, the boundary 64 is formed as an ink deposition ona non-functioning component of the structure, for example the oppositeside of the glass substrate.

Turning to FIG. 5, a representation of the pattern of the resistive ITOdeposition as well as the conduction band structuring as combined withthe shorting bar structures 60-63 and the geometric configuration of aplurality of spaced, discrete resistive elements is revealed. Thepattern by which the resistive layer region or operational region of thetablet 30 may be provided to achieve desired resistivity and drift freeperformance is revealed in general at 70, the solid rectangular patternlines representing the glass substrate. This tablet 30 geometry futherincludes a conduction band which is formed of deposited ITO inconjunction with the earlier-described shorting bar configuration. Inthis regard, a conduction band represented generally at 72 is shownpositioned intermediate the outer boundary 32 of the tablet 30 and theouter periphery of the resistive layer or grid pattern 70. Band 72 isformed of an ITO deposition represented as spaced lines 74. Over thisdeposition 72, there is positioned on earlier-described shorting barstructure 62. Looking, in particular, to the latter structure, theshorting bars are shown to include, for example, two spaced parallelbars as at 76 and 78 between which is a deposition of ITO. Similarly, anidentically shaped pair of shorting bars are shown at 80 and 82 and ashort lead 84 is seen connecting the two shorting bar structures. Theshorting bars are formed as a deposited conductive material such as asilver ink and are seen to be in electrical communication with theconduction band deposition 74. The structures of the shorting bars as at76, 78, 80 and 82 are identical with the exception of those firstcomponents at each corner electrode, for example as at 86. Noteadditionally that most of the bars are paired, i.e. 76 and 78 and thatthe ITO layer of the conduction band over which they are depositedextends outwardly between them. By comparison it may be observed thatthe initial shorting bars adjacent to the L-shaped terminal 56 aresingular as opposed to being paired and are of lesser lengthwise extent.

A similar conduction band is provided adjacent outer border 38 as at 92which is seen to be formed of an ITO deposition 94 over which theshorting bar structure 61 is deposited. This same geometry is repeatedabout all four borders 32, 34, 36 and 38 of tablet 30.

Additionally formed as an ITO deposition upon the glass substrate oftablet 30 are a plurality of spaced, discrete resistance elements. Forexample, resistance elements 100-109 are shown in electricalcommunication between the resistive layer represented at grid 70 andconduction band 72 and contact the conduction band intermediate theshorting bar structures. Note that the widthwise extent of each of theseresistive elements commencing at element 100 and extending, for example,to element 109, increases so that the impendance represented therebylowers. Generally, this increase in widthwise extent of the resistiveelements continues until the midpoint between any two adjacentterminals, for example terminals 56 and 44 or the same terminal 56 andadjacent terminal 52 (see FIG. 4). In similar fashion, a plurality ofspaced, discrete resistance elements as at 112-131 are seen to extendfrom conduction band to resistive layer grid along border 30. As before,these elements are seen to exhibit increasing widthwise dimension in theprogression thereof from element 112 through 131 and this increasingdimension continues to the resistive region periphery midpoint. Thethicknesses of these resistive elements for each of the borders and, ineffect, the resistance value thereof, is selected to effect anexhibition of a substantially uniform electric impedance of theresistive layer 70 to each of the terminals as at 44, 48, 52, and 56forms a digitizing topology generally referred to as "corner driven".Looking additionally to FIG. 6, a schematic representation of this typeof corner drive wherein the excitation signal as applied to theresistive layer is revealed in conjunction with a generalizedrepresentation of tablet 30. The general switching technique employedwith the tablet 30 is one for carrying out a difference/sum ratiocoordinate determination. Accordingly, in FIG. 6, the tablet 30 and itsresistive layer are shown of generally rectangular shape being accessedby a stylus or locator 134 at some point (x, y). The resistive of tablet30 is shown having designated x+ and x- axes as well as y+ and y- axes,the intersection therebetween being essentially at the center of therectangularly configured tablet 30.

Assuming that the coordinate system shown ranges from +1 to -1 in boththe x and y directions, a signal representing any given coordinate (x,y) pair can be determined by measuring the current and voltage valuepicked up by the locator 134 under a procedure where the alternatingvoltage source or time varying excitation source initially is applied totwo adjacent corners of the resistive layer in one coordinate directionwhile ground reference is applied to the oppositely disposed adjacentcorners. This procedure then is reversed for the first coordinatedirection and the combined readings may be used to determine onecoordinate. The procedure then is carried in the opposite coordinatesense. For example, arbitrarily designating that the output of stylus134 is to be termed XPLUS when an alternating current source is appliedalong the x+ coordinate direction at appropriate adjacent corners oftable 30 while simultaneously, ground is applied to the opposite, x-coordinate adjacent corners; arbitrarily designating XMINUS to be thesignal at stylus 134 when the opposite condition obtains, wherein thealternating current source is applied to the x-coordinate adjacentcorners of the resistive layer and ground is applied to theoppositely-disposed, x+ edge; designating YPLUS to be the signal atlocator 134 when the alternating signal source is applied to theadjacent corners of the resistive layer at the y+ coordinate and groundis applied to the opposite or y- coordinate adjacent corners; anddesignating YMINUS to be the signal derived at locator 134 when thealternating current source is effectively applied along the adjacentcorners of resistance of a resistive layer at the y- coordinate positionthereof, while ground is applied at the adjacent corners of sheet 30represented at the y+ side. With the arrangement, coordinate pairsignals may be derived, however, only four electrode locations, thecorners of the resistive area, are employed. Essentially the same typeof geometry in switching is employed for the utilization of the locator134 as the injection of current to the resistive layer.

With the arrangment shown, signal values may be employed with adifference/sum ratio, to derive paired coordinate signals for anyposition of the locator 134 on the resistive surface as follows:##EQU1##

Unlike earlier coordinate pair derivation techniques, the drivingarrangement of the instant invention is binary in form. In this regard,the y-coordinate borders do not have terminals with associated switcheswhich "float" during excitation for x-coordinate information and viceversa. Generally, the above sum/difference ratio procedure is referredto as "normalization".

FIG. 6 shows an alternating current source or excitation signal sourceat 136 coupled between groun via line 138 and to a distribution line140. Line 140 extends to one pole of binary switches 142-145. In thisregard, line 140 is seen directed to one pole of switch 142 via line 146and is directly coupled to one pole of switch 145. Similarly, a line 148connects line 140 with one pole of switch 143 and a line 150 extendingfrom line 148 is coupled to one pole of switch 144. Ground is madeavailable for the corner switching arrangement from lines 152 and 154 tothe poles of respective switches 143 and 144, while the same ground isapplied via lines 156 and 158 to one pole of respective switches 145 and142.

The selected ground or excitation source input to the resistive layertablet 50 is provided from switches 142-145 through respective drivers160-163. And these drivers, in turn, are coupled to respective terminals44, 48, 52, and 56. The same lead lines as disclosed in connection withFIG. 4 are shown coupling the terminals with the outputs of the noteddrivers 160-163. Control over switches 142-145 is developed from amicroprocessor and related I/O circuit as represented at block 166. Thecontrol inputs from the microprocessor control 166 are represented ingeneral lines by 168 and 170 leading, respectively, to solid-stateswitches 144 and 143 and via lines 168, 172, and 174 leading,respectively, to switches 142 and 145. Microprocessor control function166 is shown being associated with a non-volatile memory at block 176via line 178 as well as with the earlier-described display 42 (FIG. 4)via line 180.

The output of stylus or locator 134 is represented as being directed toinput or signal treatment circuitry via a cable 182. Typically, thetransmission of the signal via cable 182 has been found desirable toincorporate an operational amplifier as a pre-amplification stage withinthe stylus or cursor 134 itself so as to constitute the cable 182 as alow impedance source. Improved signal-to-noise ratios are achieved withsuch an arrangement. Cable 182 is seen connected to an initial inputamplification stage 814 which may, for example, be provided as anoperational amplifier. A positive input terminal of amplifier 184 iscoupled to ground through a resistor R1, while the negative inputterminal thereof is coupled to receive the signal from cable 182. Theoutput of this amplification stage at line 186 is seen to be directedthrough a conventional feedback path incorporating feedback pathresistor R2 and line 188. Line 186 is seen to be directed to a frequencyselection (f1) circuit represented within dashed boundary 190. The inputstage of the circuit 190 at 192 is provided as a voltage-to-currentconverter, the output at line 194 of which is directed through a high-Qtank circuit represented generally at 196 as incorporating an inductorL1 and capacitor C1. From the circuit 196, line 194 is seen directedthrough a buffer stage 198, the output of which at line 200 is directedto an a.c.-to-d.c. converter represented at block 202. The output ofconverter 202 at line 204 extends through a sampling or switching stagerepresented at block 206, the output of which is directed to line 208.Control over the sample switching function at block 206 is representedat line 210 as extending from the microprocessor control represented atblock 166.

Line 208 carrying the d.c. level corresponding to a given coordinatevalue is directed to an analog-to-digital conversion functionrepresented generally at 212 which is constituted by an operationalamplifier stage 214, a comparator stage 216 and a digital-to-analogconverter 218. It may be observed that line 208 carrying the noted d.c.level extends through input resistor R3 to the inverting input ofamplifier stage 214. The output of that stage at line 220 is directed toone input of the comparator stage 216. A feedback path incorporatingline 222 and resistor R4 is shown extending about the amplificationstage 214, while the non-inverting input thereof is shown coupled toground via line 224. The positive input terminal of comparator 216 iscoupled to ground via line 226, while the output thereof at line 228 isshown directed to an input to the microprocessor control 166. That samemicroprocessor control extends a controlling input to digital-to-analogconverter 218 via line 230 such that a d.c. level output is providedfrom stage 218 at line 232 which is directed through resistor R5 to asumming point represented at 234. A digital value for d.c. level at line208 thus is evolved by incrementing the output of converter 218 untilsuch time as the d.c. signal at line 232 as presented to point 234 fromresistor R4 nullifies the d.c. level at line 208. With the achievementof nullity, the output at line 228 is at a zero or reference level andthe microprocessor control 166 then accepts the digital value of theinput at line 230 as the digitized information desired. Generally, apositive output will be seen provided at line 232, while an output ofopposite polarity is provided at line 208.

The system as thus described, requiring four measurements per coordinatepair generation, i.e. two measurements in the x direction and twomeasurements in the y direction has been found to be quite adequate interms of speed of such information development. However, the rate ofcoordinate pair generation can be increased by the expedient of halvingthe number of such measurements required. To carry this out, a secondfrequency may be introduced into the system. Thus, instead of drivingone side of the resistive layer at the given excitation voltage sourceand the other at ground, one coordinate side may be driven at onefrequency and the other side at another frequency. This generates twovoltage potentials across the tablet for the given coordinate direction.In this regard, if a frequency, f1, is applied to, for example theright-hand side of the tablet 30, and a next frequency, f2, is appliedto the left-hand side in the x-coordinate direction, the frequencieswill "see" a virtual ground at the opposite coordinate side andgenerally oppositely ramping voltages will be developed simultaneouslyacross the tablet in a given elected coordinate direction. Thus, twomeasurements may be carried out in one time cycle to evolve a highcoordinate informational rate which, essentially, is limited only by thesettlement time in the analog circuitry. With the dual frequencyarrangement, for example, a coordinate pair generation rate of 200 pairsper second developed with a single frequency system may be boosted to300 coordinate pairs per second. For this alternate approach, analternate or second a.c. excitation ssource is represented in FIG. 6 at240 shown connected via dashed line 242 to ground and via dashed line244 to line 152. Thus, this second frequency, f2, may be applied vialine 152, while a different frequency, f1, may be applied in the mannerdescribed in conjunction with source 136. The resultant dual frequencyoutput then is applied through amplification stage 184 to output line186 and, simultaneously, to line 246 so as to be directed to bothfrequency selection circuit 190 and an identical circuit representedwithin dashed boundary 248 which incorporates a tank circuit as at 196tuned to frequency f2. The output of this selection circuit then isdirected via line 250 to line 208 for analog-to-digital conversionrepresented at stage 212. Switching contorls provide for the selectionof output.

For the four corner driving or accessing technique of the electrographictechnology at hand to be practical, it is necessary that the performinglinearity of the resistive layer be adequate. That is, the voltagegradients developed across the resistive surface during excitationshould be as distortion free as possible. This subject is discussed indetail in the above noted U.S. Pat. No. 4,649,232 incorporated herein byreference. With the instant invention, this development of linearitywithin resistive the region itself is achieved through utilization ofthe noted conduction bands and the discrete resistors or resistanceelements extending therefrom to the patterned resistive layer. Withoutthese features, the output or voltage gradient performance of theresistive layer for any given locator or stylus positioning will bequite distorted and unacceptable. Generally, the resistive layer willexhibit a selected resistivity as above discussed and also will exhibita corresponding conductivity. The use of a conduction band as discussedin conjunction with FIG. 4 and exemplified at 72 and 92 in FIG. 5considerably improves tablet or resistive layer performance. Topractically provide a conduction band, it is highly desirable forproduction purposes that it be formed of the same material as aresistive layer, i.e. ITO and that as high a ratio of conductancebetween the two components be developed as is practical from anelectrical performance standpiont. However, it also is desirable thatthe amount of resistive layer material between the operational area andthe conductive band be minimized and that the area of substrate taken bythe conduction band be minimized. Thus, the shorting bar techniquesdescribed in conjunction with FIGS. 4 and 5 are employed to enhance thevalue of conductivity of the conductivity bands while minimizing thesubstrate required adjacent the active resistance layer region.Generally, a ratio of 10:1 of the conductivity values of the band versusthe resistive layer is necessary, values for example of 25:1 showingconsiderable improvement over the former. Looking to FIGS. 7-10,computer plots are illustrated representing relative distortion voltagegradient grids where a noted conductivity band to resistance layerconductivity ratio of 25:1 is provided. The computer modeled plots shownin the noted figures correspond with those which will result frompositioning a locator or stylus in regular increments across the activearea of a tablet for the noted geometry. However, the resistance valuesfor the discrete resistance elements as described at 100-109 and 112-131in FIG. 5 are varied from plot-to-plot to achieve optimization. FIG. 7shows a first iteration at the noted ratio. The resultant output grid asrepresented generally at 250 shows a considerable amount of distortionabout the periphery of the readout. Grid linearity only is achieved inthe central portion of the grid 250. In FIG. 8, the values of thediscrete resistances are varied such that a grid 252 is developed inwhich linearity or squareness is achieved for a larger portion of thegrid. In FIG. 9, such linearity of grid 254 again is improved as well asat 256 in FIG. 10. However, it may be noted that the active or useablearea of the grid is somewhat severaly displaced from the border orboundary regions. FIG. 11 illustrates the effect of increasing the ratioof conductivity of the conduction band to that of the resistive layer to50:1. Note that the bow distortion about the periphery of the grid 258has been significantly reduced with this larger ratio to improveboundary utilization. Additionally, the discrete resistive elements havebeen selected so as to exhibit a uniform impendance to the cornerlocated driving terminals and the variation in values of the resistanceelements were provided as symmetrical about the half-way points betweenterminals. By employing the noted conduction band and discrete resistiveelements array, an adequate linearity may be achieved even though onlythe four corners of the rectangular resistive layer are driven asdescribed above. By incorporating the above electrographic technology inconjunction with the corrective procedure as described by Nakamura etal. in U.S. Pat. No. 4,650,926, very high and desirable resolution andaccuracy for an electrographic device can be achieved. U.S. Pat. No.4,650,926 is incorporated herein by reference.

Referring to FIG. 12, a more detailed schematic representation of thecircuitry by which the digitizer technology of the invention may beimplemented is revealed. The output of cable 182 as described inconjuction with FIG. 6 is as coupled to locator or stylus 134 isconnectable to an input line 270. Line 270, in turn, is shown coupledthrough coupling capacitor C2 and line 272 to the positive terminal of abuffer stage 274. A resistor R6 is shown coupled to ground for purposeof dissipating the d.c. component present at line 270 as blocked bycapacitor C2. The latter capacitor functions in the presence of anactive locator or stylus 134 which incorporates a pre-amplificationstage as discussed above. The output of buffer stage 274 at line 276 isdirected through base resistor R7 to the base electrode of PNPtransistor Q1. Buffer stage 274 may be provided, for example, as a typeLF357. The emitter of transistor Q1 is coupled via line 278 and resistorR8 to +15v supply and, additionally, is coupled to a feedback path forstage 274 including line 280 and defining resistors R9 and R10.

Transistor Q1 represents a current source in the noted feedback lkoop ofstage 274 such that the current entering the emitter thereof isproportioned with respect to resistor R8. The current flow from thecollector of transistor Q1 at line 282 is directed to a tank circuitformed of resistor R11, capacitor C3, and transformer 284. Therelatively high Q of an LC tank circuit as thus presented is controlledin terms of settling time by resistor R11. A transformer as at 284 isemployed in view of the -15V supply at hand and the output of thecircuits is presented to the non-inverting input of a buffer amplifier286. Amplifier 286 may, for example, be a type LF356 and the outputthereof at line 288 is seen to incorporate a feedback path includingline 290 and gain defining resistors R12 and R13. (Buffer stage 274 maybe provided, for example, as a type LF357). To assure the elimination ofany d.c. component from the signal input, an a.c. coupling comprised ofcapacitors C4 and C5 as well as resistors R15 and R16 is provided withinoutput line 288. The thus-treated signal at line 288 then is directedvia line 290 to the input of a half wave rectifier network including atype LF357 operational amplifier stage 292, the output of which at line294 is directed to a rectifying diode pair represented within dashedboundary 296. The oppositely connected diodes at boundary 296 arecoupled, in turn, via resistors R17 and R18 and line 298 to line 290 andthe output of the arrangement at resistor R17 is tapped by line 302incorporating resistor R19 for presentation to a three-pole filternetwork represented generally at 304 and comprised of capacitors C6, C7,and C8 performing in conjunction with resistors R20 and R21. With thearrangement shown, at capacitor C8 a d.c. compknent is witnessedexhibiting a level proportional to the a.c. input at line 270. This d.c.level is asserted to the non-inverting input of a type LF356 operationalamplifier 306 which provides an output at line 308 and exhibits a gaindefined by the feedback path incorporating lilne 310 and gain definingresistors R22 and R23. Stage 306 functions as a buffer to a sample andhold network represented generally at 312 which is comprised of a typeLF398 operational amplifier 314 and capacitor C9. Stage 314 is activatedfrom the microprocessor control via line 316 and functions in the logiccontrol of the system to set-up appropriate switching, sampled resultantsignals, and start the analog-to-digital convertion process. As thelatter converion process ensues, the switches are changed for alteringthe drive signal in the sequence of switching described above. Thispermits a settling time for the a.c.-to-d.c. converter function to beoptimized, it being desirable to minimize "dead time" within the analogsystem of the control circuitry. The output of sample and hold network312 is provided at line 318 and is directed to a summing point 320positioned intermediate resistors R24 and R25. The latter summing pointis seen coupled via line 322 and 324 to the inverting input of a summingamplifier 326 which may, for example, be provided as a type LF357operational amplifier. Gain of the input signal is developed by thenoted resistors R24 and R25. The output at line 322 is summed with thecorresponding output of a digital-to-analog converter 328 which may, forexample, be provided as a type PCM 5. This converter is controlleddigitally from the microprocessor control via line array 330 shownconnected to a bus connector 332. Sixteen-bit converter 328 performs inconjunction with a lower voltage level, i.e. ±5v, thus a conversion isprovided by network 334 including a voltage adjustment circuit 336 whichis coupled to +15v through resistor R26. The supply input associatedwith network 334 is filtered by capacitors as at C10 and C22 and isfurther regulated via resistors R27, R28, and R29 as well as capacitorC12. In similar fashion, a network 338, incorporating a voltageconverter 340 is shown coupled to -15v supply through resistor R30 andthe supply further is filtered by capacitor C15 and C16 as well asresistors R31 and R32. Converting device 336 may be provided, forexample, as a type LM317LZ, while device 340 may be provided as a typeLM79LO5ACM.

The d.c. output of converter 328 is provided at line 340 and is directedthrough resistor R33 to the line 324 summing input to summing amplifier326. Resistors R33 and R25 define the gain of the output of converter328. The opposite input to stage 326 is coupled to ground via line 342and the output thereof is seen provided at line 344. The gain of stage326 is established in conjunction with two feedback paths which aresignal level responsive. (R33 and R25 define the gain of the output ofconverter 328). One of the feedback paths of stage 326 is developed inconjunction with line 346, line 348, and resistor R34. The next feedbackpath is defined by line 346, diode pair 350, and resistor R25. With thearrangement shown, in the presence of very low level signals, resistorR34 represents a determination of gain, inasmuch as the ratios betweenresistors R24 and R34 and R33 and R34 are high such that an enhancedgain is developed. This permits signal discrimination improvement. Wherethe voltages involved are far apart, it is not necessary to maintain thestage 326 in saturation such that the diode pair 350 conducts and theresultant gain is set by the resistor R25. Accordingly, when thevoltages at the summing input at line 324 commence to approach andnullify each other, the feedback path essentially is through resistorR34.

Output line 344 is directed to one input of a comparator 352 having anoutput at line 354. Line 354 is coupled through pull-up resistor R35 to+5v and the stage is configured having a feedback path including lines356 and 358 along with resistors R36 and R37. The resultant output atline 354 will have an effective zero value in the presence ofcoincidence between the output of the converter stage 328 and theincoming d.c. signal. As represented at connector 360, this output isdirected to the microprocessor control function. The digitizingtechnique is one of successive approximation wherein the mostsignificant bit of device 328 initially is activated and a greater-thanor less-than comparison is made for evaluation at the computer stage.Upon coincidence of values and an effective zero output at connector360, the digital input to comparator 328 is read as the digitizedvaluation.

The microprocessor driven control of the system also includes an offsetmeasurement feature wherein any d.c. phenomena within the signaltreatment or analog portion of the circuit is evaluated through theexpedient of turning off the current supply as developed at transistorQ1 and then evaluating for such a d.c. term. Transistor Q1 is turned offby a PNP switching transistor Q2, the collector of which is coupled vialine 362 to line 276 and base of transistor Q1. The emitter oftransistor Q2 is coupled via line 364 and line 366 to +15v, while thebase thereof is coupled via line 368 to line 370. The latter connectionis seen to be positioned between resistors R38 and R39. When transistorQ2 is turned on, the base of transistor Q1 is caused to assume a high or+15v condition to switch or clamp transistor Q1 off. Transistor Q2, inturn, is controlled from NPN transistor Q3 the collector of which iscoupled to line 370 and the emitter of which is coupled via line 372 toconnector 374 representing an offset input from the microprocessorcontrol. The base of transistor Q3 is coupled via line 376 and resistorR40 to ground as well as through resistor R41 to line 364. With thearrangement, the base of transistor Q2 is at a voltage determined byresistors R40 and R41 providing a positive bias. Where the input atconnector 374 brings the emitter to a logic low at line 372, transistorQ3 will turn on to pull the base of transistor Q2 low causing it toconduct to saturation. At the latter condition occurs, transistor Q1 isturned off to cancel current flow to line 282. Under these conditions,the microprocessor may then evaluate the d.c. levels within the analogcircuitry.

Referring to FIG. 13, the a.c. excitation source or drive forapplication to the electrographic device is portrayed. In its generalperformance, a 122.88 KHz signal is derived from the microprocessorcontrol function and introduced as represented at connector 380. Theresultant a.c. sinewave is directed via line 382 through a stabilizationnetwork 384 comprised of capacitor C17 and resistor R43 to the base ofNPN transistor Q4. The emitter of transistor Q4 is coupled to ground,while the collector thereof is coupled through resistor R44 and R445 to+15v. A line 386 is connected from the midpoint of the latter resistorsto the base of PNP transistor Q5, the emitter of which is coupled to+15v through resistor R46. Transistor Q5 functions as a current sourcewhich is turned on and off by transistor Q4. The resultant a.c. currentoutput from transistor Q5 at line 388 is directed to a two-stage tank,L-C circuit represented generally at 390 and shown to be formed ofinductor 392 along with capacitors C18, C19, and resistor R47. A secondstage of the filter 390 is comprised of capacitors C20 and C21performing in conjunction with inductor 394 and resistor R48. The outputof tank circuit 390 at lines 396 is buffered at operational amplifierstage 398, the output of which at line 400 extends through diode D1 andresistor R49 to the input of a rectifier stage 402. Buffer 398 and stage402 may be provided, for example, as type LF353 operational amplifiers.Rectifier stage 402 is so configured by virtue of the connection of itsnon-inverting input via line 404 to line 406 incorporating a diode D2and resistor R50. Stabilizing capacitors additionally are provided aboutthe stage 402 as repsresented at C22 and C23. The output of stage 402 atline 408 is a d.c. signal which is directed through resistor R51 toprovide an automatic gain control (AGC) function. In this regard, line408 is seen directed to the gate of an FET transistor Q6 which isemployed as a voltage controlled resistor which is located in parllelwith the emitter resistor of transistor Q6 which, in turn, providescurrent to the tank network 390. In this regard, note that a by-passresistor R52 is positioned about transistor Q5 within line 410 andthence is directed through resistor R53 and line 412 as noted above tothe emitter of transistor Q6. The output of the filter network 390 atlines 414 and 416 is a controlled a.c. signal which is directed throughresistor R54 to an next buffer stage 418 having an output atdistribution line 420. A feedback resistor R55 is coupled between line420 and input line 416, while a stabilizing network 422 comprised ofcapacitor C24 and resistor R56 is coupled to the non-inverting input ofthe stage 14 which, in turn, may be provided as a type LF356 operationalamplifier. Line 420 carrying the a.c. output is directed to the input offour binary switches contained with a package thereof represented withinblock 424. Each of the discrete switches within block 424 is controlledfrom the microprocessor function as represented by the "drive" connector426 and the four line array 428 control associated therewith. In similarfashion, a ground is asserted from line 430 to the input of fourswitches contained within a four switch package thereof 432. The latterswitches are simultaneously controlled from the four line array 428.Switch 424 package may be provided, for example, as a type DG 211 whileswitch package 432 may be provided as a type DG 212. These switchgroupings 424 and 432 operate in parallel pairs in a fashion such thatone control input from array 428 controls two switch componentss, onecomponent opening and its mutually paired component closing. The outputsfrom the paired switches extend to four driver networks representedgenerally at 432-435 and the outputs of these driver networks aredirected to respective leads 58, 46, 50 and 54 as described inconjunction with FIG. 4. Inasmuch as each of the networks 432-435 isidentical, that at 432 is described herein and the components ofcircuits 433-435 are shown with the same numeration in successionalprimed fashion. Network 432 is shown receiving a switched output fromlines 436 and 438, the latter of which is directed to the non-invertinginput of an operational amplifier 440. The output of amplifier 440 atthe line 442 is directed through resistor R58 to line 444 at a pointintermediate diodes D3 and D4. Line 444 is seen to be in single transferrelationship with the bases of NPN transistor Q7 and PNP transistor Q8having a common emitter connection through resistors R59 and R60. Thejunction between resistors R59 and R60 is coupled with line 446 infeedback fashion to the inverting input of amplifier 440. Resistors asat R61 and R62 couple the collectors of transistors Q7 and Q8 to line444 and the transistors Q7 and Q8 are seen to be coupled at theircollectors with respective +15v and -15v supply. With the push-pullarrangement thus shown, a relatively noise immune output may be providedof desirable consistnecy at the outputs of the driver circuits. DiodesD3 and D4 provide for assured operation near the cross-over point of thesinusoidal a.c. output of the drivers during that mode of theiroperation. It may be observed that the driver networks 432-435 alsofunction to isolate the switches within groupings 424 and 432 from theresistive layer of the electrographic device.

Referring to FIG. 14A and 14B which are mutually associated inaccordance with the labeling provided thereon, the microprocessor drivencontrol features of the invention are portrayed. FIG. 14A shows amicroprocessor 1450 which may, for example, be provided as a type 8092marketed by Intel Corporation. This 16-bit device incorporates auniversal asynchronous receiver-transmission (UART) function and is seenreceiving a 7.3728 MHz clock input at its XTL1 and XTL2 input terminalsfrom a crystal 452 associated with capacitors C26 and C27. A 16-linearray 454 is seen emanating from the P3.0-P4.7 ports of device 450 whichevolves as a bus 456 which is directed through eight-line arrays 458 and460 (FIG. 14B0 to respective address latches 462 and 464. Additionally,bus 456 is seen to be connected through eight-line arrays to respectivelatches 470 and 472. Latches 462, 464, 470 and 462 may be provided, forexample, as type 74HCT373. The outputs of latches 470 and 472 arecombined into a 16-bit bus as at 474 for controlling input to thedigital-to-analog converter 328 (FIG. 12) as represented byearlier-described connector 332 which was reproduced in FIG. 14B. Theoutputs of corresponding latches 462 and 464 are directed to a 16-bitbus 476 which, in turn, extends to the A0-A14 inputs of an EPROM memory480 as well as through array 482 to an identical EPROM memory 484.Memories 480 and 484 may be provided, for example, as a type 27C256. TheD0-D7 terminals of memories 480 and 484, respectively, are coupledthrough lines arrays 486 and 488 to bus 490 which extends through buslinkage 492 to earlier-described bus 456.

The output enable (OE) terminals of address latches 462 and 464 arecoupled to ground via lines 494 and 496, while their enablement isprovided from lines 498 and 500, the latter extending to the ALEterminal of microprocessor 450 as seen in FIG. 14A. Similarly, the clear(CLR) terminals of latches 470 and 472 are coupled to +15v via lines 502and 504, the latter being coupled through resistor R63 to +5v. Theselatches additionally are enabled from lines 506 and 508.

The output enablement terminal (OE) of memory 480 is activated from line510 which extends as the output of address decoder three input NO gate512, the common inputs of which, in turn, are derived from line 514 andaddress decoder NAND gate 516, the inputs of which are coupled both to+5v and bus 476. Line 510 additionally is coupled to lines 518 and 520which extends to the inputs of a chip selection logic network shown inFIG. 14A at 522. The chip select (CE) terminals of memories 480 and 484are commonly enabled from lines 524 and 526, the latter line extendingto the write (WR) port of microprocessor 450. The bus next adjacent toline 520 at 528 is seen to extend from the HSO, P1.5-P1.7 terminals ofmicroprocessor 450 to the earlier-described offset connector 374 (FIG.12) as well as the switch drive connector described in FIG. 13 at 426and carrying the same numeration in FIG. 14B. The LCD display describedin connection with FIG. 442 again is reproduced in FIG. 14B. VDD, VL andVSS terminals of the device are coupled via three-line array to +5 v asmodified by serial resistors R64 and R65. An enable output of device 42is coupled to line 532 representing one output of selection network 522,while the data terminals D0-D7 are coupled to earlier-described buscomponent 492 via line array 534. The RS and read/write (R/W) terminalsof device 42 are seen coupled to bus 476. FIG. 14B also reveals thepresence of RS232 communications components in general at 536. Thesecomponents are in communcation with the microprocessor 450 via bus 538which extends to the P2.0, P2.1, P2.6, and P2.7 terminals thereof. Onelead from bus 538 at 540 extends through gate 542 to provide a transmitoutput at line 544. Similarly, a ready-to-send (RTS) output is providedfrom lead 546, gate 548, and line 550. The light-emitting diode (LED)552 may be illuminated in the presence of an activation of gate 548. Insimilar fashion, a clear-to-send (CTS) input to the microprocessor 450may be provided from line 554, gate 556, and line 558 to bus 538.Simultaneously with the position of the signal at line 554, an LED 560may be energized from line 562 and resistor R66. Finally, a receivedtransmission may be provided at line 564 which extends through gate 566and line 568 to bus 538.

Returning to FIG. 14A, the output of the comparator represented atconnector 360 (FIG. 12) again is represented by the same numeration asextending via line 570 to the P0.5 terminal of device 450. Similarly,the sample and hold connector as described 317 again reproduced and isseen being coupled via line 572 to the P1.1 terminal of device 450.

A non-volatile RAM 574 is provided which may be, for example, a typeS2444 and serves the function of retaining set-up instructions utilizedby the user to configure the digitizer tablet as at 30. Memory 574 isshown connected to the P1.4, P1.3, P0.6 and P1.2 terminals ofmicroprocessor 450. In essence, device 574 provides the permanence ofswitching components as earlier were employed with digitizer tablets asan adjunct to the convenience of the menu programmed configurationtechnique of the invention.

The read (RD) and write (WR) terminals of microprocessor 450 are seen tobe connected via lines 576 and 578 to the respective clear and clockterminals of a wait state generator 580 which performs a concert with asimilar device 582, both components being present, for example, as type74HCT393 devices. The Q1 output of device 582 is seen coupled throughgate 584 and line 586 to the clear terminal of device 580, while theclock input of device 582 is coupled via line 588 to network 522. Oneoutput of the latter network at line 532 is seen to extend to the Eterminal of display 42 and the arrangement shown provides a persistenceof display inasmuch as LCDs as may be employed are relatively slowdevices and a read or write wait state is required for their appropriateoperation.

Push-button input from a tracer, for example as described in U.S. Pat.No. 4,707,572 by Kable, et al. incorporated herein by reference may becoupled via five-line array 590 to the P0.0-P0.4 terminals ofmicroprocessor 450. The discrete lines within the array 590 are coupledthrough pull-up resistors shown arrayed at 592 to +5v and acorresponding array of stablizing capacitors is shown at 594.

The clock output of microprocessor 450 at line 578 is tapped by line 596for submittal to cascaded counters 598 and 560. These counters areconfigured to develop a 122.8 KHz output which is directed via line 602to the earlier connectors 380 described in conjunction with FIG. 13 andreproduced with the same numeration herein. sehe tracer or stylus whichmay be employed with the electrographic device preferably willincorporate a light-emitting diode (LED) which will apprise the operatorthat coordinate pair measurements are being made and data are beingreturned into the control system. Such an LED is driven from the P1.0port of device 450 as repesented by line 604 incorporating a pull-upresistor R67 coupled to +5v and extending through pull-up resistors R68to the base of NPN transistor Q10. The emitter of transistor Q10 iscoupled to ground, while the collector thereof is coupled via line 606incorporating Zenner diode D5 and resistor R69 to line 608 coupled, inturn, to the collector of NPN transistor Q11. The base of transistor Q11is coupled to line 606 intermediate diode D5 and resistor R69, while theemitter thereof functions as an LED drive at line 610 to the noted LED.Line 610 is seen to incorporate resistor R70.

Referring to FIG. 15A, a first component of a generalized main controlprogram under which device 450 performs is set forth in flow chartfashion. This program commences as represented at block 620 with aninitialization of stack pointers and an initialization of and, ineffect, clearing out of memory retained variables. The program thenproceeds as represented at block 622 to carry out the intialization ofthe all hardware components including such elements as serial ports andthe like. Next, as represented at block 624, the operating orconfiguration parameters of the tablet as retained in non-volatile RAM574 are read. These configurations variable will include Baud ratescaling factors determining whether English or metric units have beenelected, the coordinate speed, for example 50 coordinates per second,100 coordinates per second and the like. Next, the mode of operation maybe elected whether its stream mode wherein all data are continuouslycollected or point mode wherein data are collected at the depression ofa locator retained push-button or the like. Next, an emulation electionas to the particular form or manufacturer configuration of the digitizeris selected. Further, a determination is made as to whether the data arerecorded in ASCII or binary format.

Next, as represented at block 626, the display 42 is set-up for a bargraph readout which provides a visual feedback that the system isoperating, the bar position display representing relevant position ofthe locator device on the operational surface. The bars, in effect,represent a percent of full scale of position of the locator on thesurface of the digitzer device. This form of display is distinguishedfrom the positioning of the locator, tracer, or stylus at a menu area ofthe working surface typically located near housing 40. Next, asrepresented at block 628, the drive switches as described at 424 and 432in FIG. 13 are set-up and, the program then progresses to commence a1.25 millisecond interrupt cycle as represented at block 630. This ispredicated upon a coordinate pair generation rate of 200 per second.

Following the above general initiation procedures, the program thenproceeds to the inquiry as represented at block 632 wherein adetermination is made as to whether coordinate data are present forprocessing. In the event they are not, then as represented by loop line634, the system dwells until such data are present. In the eventcoordinate date are available, then as represented at line 636 and block638, the earlier-described sum/difference normalization procedures arecarried out. The program then continues as represented at block 640 tocarry out error correction of the compiled data. This form of errorcorrection is described in detail in U.S. Pat. No. 4,650,926 (supa).Following error correction, as represented at decision block 642, adetermination in made as to whether the locator has been positioned inthe menu area of the digitizer tablet. This menu area performs inconjunction with display 42 to carry out the earlier-noted configurationof set-up of the digitizer tablet.

In the event that the locator is not positioned in the noted menu area,then as represented by line 644 and block 646, the data are scaled withrespect to English or metric units. Next, as represented at decisionblock 648, a determinatiion is made as to whether the data should bepresented as an output. In the latter regard, a determination is made asto whether stream mode of operation or point mode is present. In thelatter condition, the data are not outputted until such time as a cursoror stylus locator button is depressed by the operator. In the event thatthe data should not be presented as an output, then as represented byline 650 and node A, the program returns to line 652 and the resultantinquiry as to whether data are present as earlier-described inconjunction with inquiry block 632.

Where the inquiry at block 648 is affirmative, then as represented atline 652 and block 654, the data are complied in appropriate format,i.e. ASCII or binary and the program progresses to the instructions atblock 656 wherein the data are sent over a serial output port to anassociated computer. The program then continues as represented at line658 and node A to the earlier-described line 652 and inquiry block 632.

Where the determination at block 642 is the affirmative indicating thatthe locator is within the menu area, then as represented at line 660 andnode C, the program proceeds as represented at corresponding line 662and node C in FIG. 15B. Line 662 as shown directed to the instructionsat block 664. Generally, the menu area can be constitued as a smallsquare outside of the working area represented at boundary 64 but insideof the conduction bands and adjacent the housing 40 (see FIG. 4). Theinstructions at block 664 provide for the presentation at display 42 ofthe first prompt which generally will instruct the operator to press afirst button located upon the cursor or locator device. This furtherfunctions to initialize a display pointer. The program then proceeds asrepresented at block 666 to set the menu active flag which then permitsthe operator to move the cursor or locator into the main active areawithin boundary 64 and move the device in one direction or another toeffect the scanning of the configuration menu. This generally is carriedout with simple right movement of the cursor upon the resistive layersurface or left movement, i.e. if the movement is to the right andincrementation is up, and if the movement is to the left theincrementation is down in a menu utilization sense.

Looking momentarily to FIG. 16, a generalized menu tree structure isportrayed, the menu being entered as shown to achieve a first level inthe tree. Items within the level are labelled display state (DS) 1-4 andwill incorporate such board level selections as change or the like. Theoperator moves the cursor or locator to elect one of these level 1selections and, for example, where it indicates that a change isdirected, i.e. at item DS1, then level 2 is accessed and the noteddisplay pointer moves downward in memory in accordance with theselections. At level 2 under the selection of change DS1, it may beobserved that items DS5 through DS7 may be elected by cursor or locatormovement. Elections have may provide for mode selection, i.e. stream orpoint, coordinate pair rates and data formatting. The menu structurethen may continue as shown at level 3 and item DS (1+7+1) and to furtherlevels as at level 4 and the selection of items as a DS(N).

Returning to FIG. 15B, following the setting of the menu active flag asrepresented at block 666, the program proceeds to the inquiry at block668 wherein a determination is made as to whether a push-button on thelocator has been depressed or is active. If such button has not beendepressed, then as represented at line 670 and inquiry block 672, adetermination is made as to whether motion of the locator has occurredwithin the digitizing region surrounded by boundary 64 since the lastbutton activation. If motion flag is not set, then as represented byloop line 674, the program returns to the inquiry at block 668 to awaitpush-button activity. Where no motion or push-button activations arepresent, the program may be exited by menu selection of a "digitize" or"exit" instruction.

Where the motion flag has been set and the inquiry at block 672 resultsin an affirmative determination, then as represented at line 676, adetermination is made as to whether the motion of the locator is to theright or to the left. Where it is to the right, then as represented atblock 678, the display pointer is incremented. Correspondingly, wherethe motion is to the left, as represented at block 680, the displaypointer is decremented. Following such pointer alteration, asrepresented at line 682 and block 684, the pointer location is used toindex to a new message for readout at display 42. The program then loopsas represented at line 686 to again await push-button activity asrepresented at inquiry block 668. In general, with each alteration ofthe display message, a new sub-routine is accessed to carry out therequisite display state for illustration at display 42 and, a subroutinerepresenting an action state is carried out which reconfigures themicroprocessor 450.

Where the inquiry at block 668 is in the affirmative determining that apush-button at the locator has been actuated, then as represented atline 688 and node B the program continues as represented at line 690 and692 to set the display 42 and the corresponding action state access hasno activity associated with it, i.e. it is a null, a form of exit iscarried out as represented in line 698 and node D. Node D is seen tore-enter the program as shown in FIG. 15B at line 700 at which point adetermination is made as to whether the push-button at the locator hasbeen activated. Where action state is not a null, then as represented atline 702 and block 704 a test is made as to whether the action state isan exit. In the event that it is, then as represented at line 706 andnode A, the program returns to line 652 and the entry to a determinationas represented at block 632 as to whether coordinate data are availablefor processing. Where the inquiry at block 704 determines that an exitstate is not at hand, then as represented at line 708 and block 710 theselected action state is executed and, as represented at line 712, theprogram progresses to earlier-described node D represented at line 700in FIG. 15B wherein the inquiry at block 668 again is carried out.

An interrupt program as illustrated in conjunction with FIGS. 17A and17B operates in parallel with the main program represented by FIGS.15A-15C. Looking to FIG. 17A, the interrupt routine is shown entering atline 720, such entry, for example, commencing with the start of the 1.25Mg interrupt cycle as discussed in conjunction with block 630 in FIG.15A. Line 720 leads to the instructions at block 722 providing for thesaving of register retained data during the interrupt interval. Theprogram then continues as represented at block 724 to commence the 1.25Mg interrupt timing and, as represented at block 726, the sample andhold circuit is set at the hold mode as represented at connector 317.The program then proceeds to the inquiry represented at block 728wherein a determination is made as to whether it is time to carry out anoffset measurement. The offset measurements are carried out, forexample, once every 64,000 cycles. In the event such time is at hand, asrepresented at line 730 and block 732, the analog circuit is set for theoffset mode with appropriate inputs through connector 374(FIG. 12). Theprogram then proceeds as represented at line 734. Where the inquiry atblock 728 determines that the time is not appropriate for an offsetmeasurement, then as represented at line 736 and block 738, the driveswitches are set for the next state or next mode of measurement. Theprogram then continues as represented at line 740 and block 742 to carryout an analog-to-digital conversion. Results of this conversion aresaved a represented at block 744 and the results of any push-buttonstatus are checked and saved. The program then continues as representedat node A andline 748 in FIG. 17B. Line 748 leads to the inquiry atblock 750 determining whether the menu flag has been sent by vitue ofthe earlier discussed movement of the locator or tracer to the menublock at the resistive surface. Where the menu flag has been sent, thenas represented at line 752 and block 754 a determination is made as towhether there has been movement since last intyerrupt. In the event thatthere has, then as represented at line 756 and block 758, a motion flagis set and the program continues as represented at line 760 and 762.Where there has been no movement of the locator as determined by theinquiry at block 754, the program continues as represented at line 762.Where a negative determination is made in conjunction with the querry atblock 750 and the menu flag is not set, then the register data arerestored as set forth in the instructions at block 766, and asrepresented at block 768, the main routine from which the interruptoccurred is re-accessed.

As indicated earlier herein, the digitizer technology of the inventionalso is capable of operating in a mode wherein excitation current issupplied from the locator or stylus itself. Looking to FIG. 18, adigitizer tablet is shown in general at 780. Tablet 780 is configuredessentially identically as tablet 30 described above, however, thecorner terminals or electrodes now are coupled with a receiving deviceor current-to-voltage converter. FIG. 18 shows the tablet 780 beingdirectly accessed by contact with a stylus or similar locator 782.Stylus 82 is fed from an a.c. source of excitation represented at 784,the output of which extends via line 786 to a driver 788 thence viacable 790 to the contacting devcie 782. The corner terminals of tablet780 are accessed via lines 792-795 which, respectively, extend tocurrent-to-voltage receiving devices or converters 798-801. Thesedevices 798-801 also exhibit a virtual ground to current injected to theresistance layer via device 782. The outputs of converters 798-801 aredirected to respective solid-state switches 804-807 which, in turn, arecontrolled by a microprocessor driven control circuit represented atblock 810. In this regard, the control is represented by lines 812, 814,816, and 818. The voltage signal outputs collected from switches 804-807are shown directed to line 820 from switch 807; to line 822 and 820 fromswitch 804; to line 824 and 820 from switch 805, and to lines 826 and820 from switch 806. Line 820 is seen to be directed to one input of anamplification stage 830, the non-inverting input of which is coupled toground through resistor R74 and the output of which at line 832 iscoupled through feedback resistor R75 to input line 820. Output line832, as before, is directed to a frequency selection network representedgenerally within dashed boundary 834 and which includes an initialvoltage-to-current converter stage represented at 836, the output ofwhich at line 838 is directed to a tank circuit including inductor L2and capacitor C30. Line 838 is seen being directed to a buffer stage 840and thence to an a.c.-to-d.c. converter represented at block 842. Theresultant d.c. level then is directed to a sample and hold circuitrepresented at block 844 which is under the control of themicroprocessor control function 810 as represented by line 846. Asbefore, the output of sample and hold circuit 844 at line 846 isdirected through a resistor R76 to a summing point 848 and thence to theinput of a summing amplifier stage represented generally at 850. Stage850 includes operational amplifier 852, the non-inverting input to whichis coupled to ground via line 854 and the output of which at line 856 iscoupled to a feedback path represented at line 858 which incorporates aresistor R77. Summing point 858 also receives a d.c. level signal ofopposite polarity through resistor R78 within line 860. Line 860receives a d.c. level signal from digital-to-analog converter 862 whichis controlled, in turn, from microprocessor control function 810 asrepresented by line 864. The digitizing arrangement work, as before,through successive tests until a null condition is received at summingpoint 848. The results of this procedure are tested by a comparator 866having its inverting input coupled with line 856 and its non-invertinginput coupled with ground as represented at line 868. The output of thecomparator at line 870 is redirected to the microprocessing function810. As before, control function 810 additionally operates inconjunction with non-volatile NOV RAM to preserve tablet configurationas represented at block 872 and line 874. Further, the earlier-describedLCD display shown in FIG. 4 at 42 is represented in the instantembodiment at block 876 which is shown associated with the controlfunction at block 810 by a line 878.

Since certain changes may be made in the above-described system, method,and apparatus without departing from the scope of the invention herein,it is intended that all matter contained in the description thereof orshown in the accompanying drawings shall be interpreted as illustrativeand not in a limiting sense.

I claim:
 1. Apparatus of a type wherein a surface is selectivelyaccessed with respect to positional data, comprising:an insulativesubstrate; a resistive layer supported upon said substrate having anoperational region extending within an operational periphery ofpredetermined geometric pattern and configured to exhibit predeterminedvalues of conductivity and resistivity; said operational periphery beingspaced inwardly from an outer boundary; mutually spaced terminalssupported upon said substrate positioned adjacent said outer boundaryand the corners of said geometric pattern; means defining a conductionband exhibiting enhanced conductivity with respect to said operationalregion conductivity supported upon said substrate intermediate saidouter boundary and said operational periphery; a plurality of spaced,discrete resistance elements, each in electrical communcationintermediate said conduction band and said resistive layer and eachhaving a resistance value selected to effect exhibition of asubstantially uniform electrical impedance of said layer to each saidterminal; an excitation signal source; a ground reference; swich meansactuable for applying said ground reference to first select ones of saidterminals while, simultaneously applying said excitation signal sourceto second ones of said terminals oppositely disposed from said firstones; and control means for actuating said switch means to effectderivation of positional data modes.
 2. The apparatus of claim 1 inwhich said value of each said discrete resistor component is selected incorrespondence wiht the extent of voltage gradient distortion fromlinearity otherwise present at the location thereof during a said switchmeans actuation.
 3. The apparatus of claim 1 in which said enhancedconductivity of said conduction band is selected having a ratio ofconductivity with respect to the conductivity of said operational regionconductivity of at least about 10:1.
 4. The apparatus of claim 3 inwhich:said resistive layer and said conduction band are codepositedhaving substantially equivalent thicknesses upon said substrate; andsaid conduction band includes a plurality of shorting bars selected toderive said ratio of conductivity.
 5. The apparatus of claim 3 inwhich:said resistive layer, said conduction band and said resistiveelements are formed of indium tin oxide codeposited upon said substrate;and said conduction band includes a plurality of shorting barsconfigured to derive said ratios of conductivity.
 6. The apparatus ofclaim 4 in which:said conduction band is formed on said substrate as anelongate layer of indium tin oxide and said shorting bars are formed ofsubstantially regularly spaced pairs of metallic conductors arrangedtransversely to said elongate layers.
 7. The apparatus of claim 4 inwhich each said discrete resistive element is codeposited upon saidsubstrate having said equivalent thickness and a widthwise extentselected to provide said resistance value.
 8. The apparatus of claim 1in which said predetermined geometric pattern is rectangular having foursaid corners.
 9. The apparatus of claim 1 in which said switch meansincludes:a solid-state driver network coupled with each said terminaland responsive to a select drive input to effect application of saidground reference and excitation signal source; and solid-state switchmeans coupled with said excitation signal source and said groundreference, responsive to said control means actuation for providing saidselect drive output to each said driver network.
 10. The apparatus ofclaim 1 in which said enhanced conductivity of said conduction band isselected to establish a ratio of the said conductivity thereof withrespect to the said conductivity of said operational region of about25:1.
 11. The apparatus of claim 1 in which said enhanced conductivityof said conduction band is selected to establish a ratio of the saidconductivity thereof with respect to the said conductivity of saidoperational region of about 50:1.
 12. Apparatus of a type wherein asurface is selectively accessed with respect to positional data,comprising:an insulative substrate; a resistive layer supported uponsaid substrate having an operational region extending within anoperational periphery of predetermined geometric pattern and configuredto exhibit predetermined values of conductivity and resistivity, saidoperational periphery being spaced inwardly from an outer boundary;mutually spaced terminals supported upon said substrate and positionedadjacent said outer boundary and the corners of said predeterminedgeometric pattern to develop positional data modes; means defining aconduction band exhibiting enhanced conductivity with respect to saidoperational region conductivity, supported upon said substrateintermediate said outer boundary and said operational periphery; aplurality of spaced discrete resistance elements, each in electricalcommunication intermediate said conduction band and said resistive layerand each having a resistance of value selected to effect exhibition of asubstantially uniform electrical impedance of said layer to each saidterminal; a time varying excitation signal source for providing a firstsignal at a first select frequency and a secon signal at a second selectfrequency; switch means actuable for applying said first signal to firstselect ones of said terminals while, simultaneously, applying saidsecond signal to second select ones of said terminals oppositelydisposed from said first ones; and control means for actuating saidswitch means to effect derivation of said positional data modes.
 13. Theapparatus of claim 12 in which said enhanced conductivity of saidconduction band is selected having a ratio of conductivity with respectto the conductivity of said operational region conductivity of at leastabout 10:1.
 14. The apparatus of claim 13 in which:said resistive layerand said conduction band are codeposited having substantially equivalentthicknesses upon said substrate; and said conduction band includes aplurality of shorting bars selected to derive said ratio ofconductivity.
 15. The apparatus of claim 13 in which:said resistivelayers, said conduction band and said resistive elements are formed ofindium tin oxide codeposited upon said substrate; and said conductionband includes a plurality of shorting bars configured to derive saidratios of conductivity.
 16. The apparatus of claim 12 furthercomprising:locator means movable about said resistive layer in adjacencytherewith at positions with respect thereto to provide position signalsdeveloped therefrom of said first and second select frequencies; signaltreatment means responsive to said position signals for effecting theamplification thereof to provide corresponding first and secondamplified signals; first filter means for filtering said first amplifiedsignals in correspondence with said first frequency to provide firstfiltered signals; second filter means for filtering said secondamplified signals in correspondence with said second frequency toprovide second filtered signals; and converter means for converting saidfirst and second filtered signals to corresponding first and second d.c.level position signals; and digital converter means for converting saidfirst and second d.c. level position signals to corresponding first andsecond digital position signals.
 17. Electrographic apparatus,comprising:an insulative substrate; a resistive layer supported uponsaid insulative substrate and extending in an x-coordinate sense betweenfirst parallel, spaced-apart borders and in a y-coordinate sense betweensecond parallel, spaced-apart border to provide a rectangular resistivelayer region having four corners and configured to exhibit predeterminedvalues of resistivity and conductivity, said resistive layer regionbeing spaced inwardly from an outer boundary; a terminal supported uponsaid substrate adjacent said outer boundary for interaction with saidresistive layer region at each said corner; means defining an elongateconduction band exhibiting predetermined enhanced conductivity withrespect to said conductivity of said resistive layer region, supportedupon said substrate intermediate said outer boundary and said first andsecond parallel, spaced-apart borders; a plurality of discrete, spacedresistance elements, each in electrical communication intermediate saidconduction band and said resistive layer region and each having a valueof resistance selected to effect exhibition of a substantially uniformelectrical impendance of said region to each said terminal an excitationsignal source; a ground reference; switch means coupled with saidterminals, said source and said ground reference and actuable toselectively apply said excitation signal and ground reference to saidterminals; locator means movable into adjacency with said resistivelayer for reacting therewith to develop position signals; and controlmeans for actuating said switch means during a first data mode to applysaid ground reference and excitation signal to first and second pairs ofsaid terminals selected in said x-coordinate sense and, to apply saidground reference and excitation signal to third and fourth pairs. ofsaid terminals selected in said y-coordinate sense during a second datamode, and including signal treatment means responsive to said positionsignals derived during said first and second data modes for derivingrespective x-coordinate and y-coordinate signals.
 18. The electrographicapparatus of claim 17 in which said enhanced conductivity of saidconductor band is selected to establish a ratio of the said conductivitythereof with respect to the said conductivity of said resistive layerregion of at least about 10:1.
 19. The apparatus of claim 18 inwhich:said resistive layer and said conduction band are codepositedhaving substantially equivalent thicknesses upon said substrate; andsaid conduction band includes a plurality of shorting bars selected toderive said ratio of conductivity.
 20. The apparatus of claim 18 inwhich:said resistive layer, said conduction band and said resistiveelements are formed of indium tin oxide codeposited upon said substrate;and said conduction band includes a plurality of shorting barsconfigured to derive said ratios of conductivity.
 21. The apparatus ofclaim 20 in which said shorting bars are formed of substantiallyregularly spaced pairs of thin metallic conductors arranged transverselyto the lengthwise extend of said elongate conduction band.
 22. Theapparatus of claim 17 in which said switch means includes:a solid-statedriver network coupled with each said terminal and responsive to aselect drive input to effect application of said ground reference andexcitation signal source; and solid-state switch means coupled with saidexcitation signal source and said ground reference, responsive to saidcontrol means actuation for providing said select drive output to eachsaid driver network.
 23. Electrographic apparatus, comprising:aninsulative substrate; a resistive layer supported upon said insulativesubstrate and extending in an x-coordinate sense between first parallel,spaced-apart borders and in a y-coordinate sense between secondparallel, spaced-apart borders to provide a rectangular resistive layerregion having four corners and configured to exhibit predeterminedvalues of resistivity and conductivity, said resistive layer regionbeing spaced inwardly from an outer boundary; a terminal supported uponsaid substrate adjacent said outer boundary for interaction with saidresistive layer region at each said corner; means defining an elongateconduction band exhibiting enhanced conductivity with respect to saidconductivity of said resistive layer region, supported upon saidsubstrate intermediate said outer boundary and said first and secondparallel, spaced-apart borders; a plurality of discrete, spacedresistive elements, each in electrical communication intermediate saidconduction band and said resistive layer region and each having a valueof resistance selected to effect exhibition of a substantially uniformelectrical impedance of said region with respect to each said terminal;an excitation signal source deriving a first signal at a first selectfrequency and a second signal at a second select frequency; switch meanscoupled with said terminals and said source and actuable to selectivelyapply said first and second excitation signals to said terminals;control means for actuating said switch means during a first data modeto apply said first and second signals to first and second pairs of saidterminals selected in said x-coordinate sense and to apply said firstand second signals to third and fourth pairs of said terminals selectedin said y-coordinate sense during a second data mode, and includingsignal treatment means responsive to said position signals derivedduring said first and second data modes for deriving respectivex-coordinate and y-coordinate signals.
 24. The electrographic apparatusof claim 23 in which said enhanced conductivity of said conduction bandis selected to establish a ratio of the said conductivity thereof withrespect to the said conductivity of said resistive layer region of atleast about 10:1.
 25. The apparatus of claim 24 in which:said resistivelayer and said conduction band are codeposited having substantiallyequivalent thicknesses upon said substrate; and said conduction bandincludes a plurality of shorting bars selected to derive said ratio ofconductivity.
 26. The apparatus of claim 24 in which:said resistivelayer, said conduction band and said resistive elements are formed ofindium tin oxide codeposited upon said substrate; and said conductionband includes a plurality of shorting bars configured to derive saidratios of conductivity.
 27. The apparatus of claim 26 in which saidshorting bars are formed of substantially regularly spaced pairs of thinmetallic conductors arranged transversely to the lengthwise extent ofsaid elongate conduction band.
 28. The apparatus of claim 23 in whichsaid control means signal treatment means comprises:input amplifiermeans responsive to said position signals for effecting theamplification therof to provide corresponding first and second amplifiedsignals; first filter means for filtering said first amplified signalsin correspondence with said first frequency to provide first filteredsignals; second filter means for filtering said second amplified signalsin correspondence with said second frequency to provide second filteredsignals; converter means for converting said first and second filteredsignals to corresponding first and second d.c. level position signals;and digital converter means for converting said first and second d.c.level position signals to corresponding first and second digitalposition signals representing respective said x-coordinate andy-coordinate signals.
 29. Apparatus of a type wherein a surface isselectively accessed with respect to positional data, comprising:aninsulative substrate; a resistive layer supported upon said substratehaving an operational region extending within an operational peripheryof predetermined geometric pattern and configured to exhibitpredetermined values of conductivity and resistivity; said operationalperiphery being spaced inwardly from an outer boundary; mutually spacedterminals supported upon said substrate, positioned adjacent said outerboundary the corners of said geometric pattern; means defining anelongate conduction band exhibiting enhanced conductivity with respectto said operational region conductivity supported upon said substrateintermediate said outer boundary and said operational periphery; aplurality of spaced, discrete resistance elements, each in electricalcommunication intermediate said conduction band and said resistive layerand each having a resistance of value selected to effect exhibition of asubstantially uniform electrical impedance of said layer to each saidterminal; an excitation signal source; locator means coupled with saidexcitation signal source and movable into contacting adjacency with saidresistive layer for applying said source thereto at a select location;current to voltage converter means coupled with each said terminal,exhibiting a virtual ground thereto and having position output signalsin response to said source application by said locator means; switchmeans actuable for collecting select said position output signals inaccordance with predetermined positional data modes; and control meansfor actuating said switch means in accordance with said data modes andfor treating said collected position output signals to derive x- andy-coordinate signals corresponding with said locator means selectlocation.
 30. The apparatus of claim 29 in which said enhancedconductivity of said conduction band is selected having a ratio ofconductivity with respect to the conductivity of said operational regionconductivity of at least about 10:1.
 31. The apparatus of claim 30 inwhich:said resistive layer, said conduction band, and resistanceelements are codeposited upon said substrate having substantiallyequivalent thicknesses; and said conduction band is elongate andincludes a plurality of shorting bars selected to derive said ratio ofconductivity.
 32. The apparatus of claim 31 in which said shorting barsare formed of substantially regularly spaced pairs of thin metallicconductors arranged transversely to the lengthwise extent of saidelongate conduction band.
 33. Electrographic apparatus, comprising:aninsulative substrate; a resistive layer supported upon said insulativesubstrate and extending in an x-coordinate sense between first parallel,spaced-apart borders and in a y-coordinate sense between secondparallel, spaced-apart borders to provide a rectangular resistive layerregion having four corners and configured to exhibit predeterminedvalues of resistivity and conductivity, said resistive layer regionbeing spaced inwardly from an outer boundary; a terminal supported uponsaid substrate adjacent said outer boundary for interaction with saidresistive layer region at each said corner; means defining an elongateconduction band exhibiting enhanced conductivity with respect to saidconductivity of said resistive layer region, supported upon saidsubstrate intermediate said outer boundary and said first and secondparallel, spaced-apart borders; a plurality of discrete, spacedresistance elements, each in electrical communication intermediate saidconduction band and said resistive layer region and each having a valueof resistance selected to effect exhibition of a substantially uniformelectrical impendance of said region to each said terminal; anexcitation signal source; locator means coupled with said excitationsignal source and movable into adjacency with said resistive layer forreacting in signal transfer relationship therewith at a select location;current to voltage converter means coupled with each said terminal,exhibiting a virtual ground thereto and having position output signalsin response to said locator means reaction; switch means actuable forcollecting select said position output signals; and control means foractuating said switch means during a first data mode to effectcollection of said position output signals from first and second pairsof said terminals selected in said x-coordinate sense and to effectcollection of said position output signals from third and fourth pairsof said terminals selected in said y-coordinate sense during a seconddata mode, and including signal treatment means responsive to saidcollected position signals derived during said first and second datamodes for deriving respective x-coordiante and y-corrdiante signals. 34.The apparatus of claim 33 in which said enhanced conductivity of saidconduction band is selected having a ratio of conductivity with respectto the conductivity of said operational region conductivity of at leastabout 10:1.
 35. The apparatus of claim 34 is which:said resistive layer,said conduction band, and resistance elements are codeposited upon saidsubstrate having substantially equivalent thicknesses; and saidconduction band is elongate and includes a plurality of shorting barsselected to derive said ratio of conductivity.
 36. The apparatus ofclaim 34 in which said shorting bars are formed of substantiallyregularly spaced pairs of thin metallic conductors arranged transverselyto the lengthwise extent of said elongate conduction band.
 37. Adigitizer tablet of a variety wherein an electrically active surface isaccessed by a locator to effect the generation of coordinate pairsignals which are converted to coordinate pair digital values by asignal treatment circuit and wherein a microprocessor having memoryconverts said digital values to digital outputs in correspondence withoperator selected received configuration parameters, the improvementcomprising:a readout mounted upon said tablet for observation by saidoperator; a menu signal region designated upon said active surface andaccessible in signal transfer relationship by said locator; said memoryretaining said configuration parameters including mode of operation,scale units and coordiante speed; said microprocessor being responsiveto said signal tranfer at said menu signal region for effecting a menuselection display at said readout for prompting said operator to selectderived said configuration parameters by select movement of said locatorupon said active surface.
 38. The method for converting voltage gradientdistortion from rectilinearity in an electrographic device formed of aninsulative substrate supporting a resistive layer of rectangular shapewithin a predetermined periphery of parallel borders, said layerexhibiting predetermined resistivity and corresponding conductivity andhaving access terminals at each corner of said rectangualr shapecomprising the steps of:providing four elongate narrow conduction bandsof conductivity enhanced by ratio of at least 10:1 with respect to thesaid conductivity of said resistive layer, substantially parallel withand in spaced adjacency from each said resistive layer parallel borderand in electrical communication with adjacent said terminals; andproviding a plurality of discrete, spaced resistive componentsintermediate each said conduction band and an adjacent said parallelborder, each said resistive component having a resistance value selectedsuch that the impedances witnessed between each and the said terminalclosest thereto are substantially equal.
 39. The method of claim 38wherein each said conduction band is provided as a deposit ofindium-tin-oxide and said ratio or conductivity is developed by theprovision of a plurality of spaced shorting bars in electricalcommunication therewith.
 40. The method of claim 39 in which saidshorting bars are configured substantially as pairs of spaced barsperpendicular to said elongate conduction band and having saidconduction band indium-tin-oxide deposited intermediate each said pair.41. The method of claim 38 in which said ratio is about 50:1.
 42. Themethod of claim 38 wherein said resistance components are provided asdeposits upon said substrate of indium-tin-oxide having thicknessselected to derive each said resistance value.